1. Field of the Invention
The present invention relates to inverter circuits, and particularly to the configuration of a circuit that suppresses noise generated by switching operations of a power semiconductor switch, and that prevents erroneous operations from occurring due to the noise.
2. Description of the Related Art
In a conventional inverter circuit, in order to suppress noise generated by switching operations, in a high-potential-side arm and a low-potential-side arm, each of which includes a semiconductor switch and a driving circuit for driving the semiconductor switch, a noise-suppression circuit is provided between the semiconductor switch and the driving circuit. Reference is made, for example, to FIG. 1 of Japanese Patent Publication 23768/2003. The noise-suppression circuit is, for example, series-connected between the gate and the emitter of a semiconductor switch (IGBT: insulated gate bipolar transistor), and configured with: diodes D101 and D102 that apply the driving direct-current voltage from the driving circuit; a first set of resistors R103 and R104 that divide the driving direct-current voltage; a first switch SW101 whose conduction is controlled by the divided driving direct-current voltage; a second set of resistors R100 and R102 that are series-connected between a power source and the emitter of the semiconductor switch (IGBT), and that divide the power source voltage according to the switching state of the first switch SW101; and a second switch SW102 whose conduction is controlled by the divided power source voltage. See Japanese Patent Publication 23768/2003 (Pages 4 and 5, and FIG. 1).
Because the conventional inverter circuit is configured as described above, there has been a problem in that, while the first switch SW101 in the noise-suppression circuit is ON, the positive and negative voltages of the power source Vcc for driving the gate are connected via the resistor R101 in the second set of resistors, so that the current flows, such that power loss occurs in the resistor R100 and the resistor generates heat.
In addition, if the value of the resistor R100 in the second set of resistors were set to a large value in order to reduce the heat generated, the switching time of the second switch SW102 would be prolonged. There has been another problem in that, when the inverter circuit is operated as an orthogonal transformation circuit of PWM (pulse width modulation) control type, for example, the all-off period (dead time) of the semiconductor switches in the high-potential and low-potential side semiconductor switches must be prolonged by the switching duration of the second switch SW102, which reduces the voltage utilization factor (the value of the ac voltage) for that duration.